A 58-63.6GHz Quadrature PLL Frequency Synthesizer in 65nm CMOS
نویسندگان
چکیده
This paper proposes a 60GHz quadrature PLL frequency synthesizer that has a tuning range capable of covering the whole band specified by the IEEE802.15.3c with exceptional phase noise. The synthesizer is constructed using a 20GHz PLL that is coupled with a frequency tripler to generate the 60GHz signal. The 20GHz PLL generates a signal with a phase noise as low as −106dBc/Hz using tail feedback to improve the phase noise. The proposed 60GHz ILO uses a combination of parallel and tail injection to enhance the locking range by reducing the Injection Locked Oscillator (ILO) current at the moment of injection. Both the 20GHz PLL and the ILO were fabricated using a 65nm CMOS process and measurement results show a phase noise of −96dBc/Hz at 60GHz while consuming 77.5mW from a 1.2V supply. To to author’s knowledge this phase noise is about 20dB better then recently reported QPLL and about 10dB compared to differential PLL operating at similar frequency.
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